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SN54HC165, SN74HC165 8 BIT PARALLEL LOAD SHIFT REGISTERS
SCLS116E - DECEMBER 1982 - REVISED SEPTEMBER 2003
D D D D D
Wide Operating Voltage Range of 2 V to 6 V Outputs Can Drive Up To 10 LSTTL Loads Low Power Consumption, 80-A Max ICC Typical tpd = 13 ns 4-mA Output Drive at 5 V
SN54HC165 . . . J OR W PACKAGE SN74HC165 . . . D, DB, N, NS, OR PW PACKAGE (TOP VIEW)
D D D D D
Low Input Current of 1 A Max Complementary Outputs Direct Overriding Load (Data) Inputs Gated Clock Inputs Parallel-to-Serial Data Conversion
SN54HC165 . . . FK PACKAGE (TOP VIEW)
SH/LD CLK E F G H QH GND
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VCC CLK INH D C B A SER QH
E F NC G H
4 5 6 7 8
3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
CLK SH/LD NC VCC CLK INH D C NC B A
NC - No internal connection ORDERABLE PART NUMBER SN74HC165N SN74HC165D SN74HC165DR SN74HC165DT SN74HC165NSR SN74HC165DBR SN74HC165PW SN74HC165PWR SN74HC165PWT SNJ54HC165J SNJ54HC165W SNJ54HC165FK SNJ54HC165J SNJ54HC165W HC165 HC165 HC165 HC165
On products compliant to MIL PRF 38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
description/ordering information
The 'HC165 devices are 8-bit parallel-load shift registers that, when clocked, shift the data toward a serial (QH) output. Parallel-in access to each stage is provided by eight individual direct data (A-H) inputs that are enabled by a low level at the shift/load (SH/LD) input. The 'HC165 devices also feature a clock-inhibit (CLK INH) function and a complementary serial (QH) output. ORDERING INFORMATION
TA PDIP - N PACKAGE Tube of 25 Tube of 40 SOIC - D -40C to 85 C -40 C 85C SOP - NS SSOP - DB Reel of 2500 Reel of 250 Reel of 2000 Reel of 2000 Tube of 90 TSSOP - PW CDIP - J -55 C 125C -55C to 125 C CFP - W LCCC - FK Reel of 2000 Reel of 250 Tube of 25 Tube of 150 Tube of 55 TOP-SIDE MARKING SN74HC165N
SNJ54HC165FK Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2003, Texas Instruments Incorporated
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QH GND NC QH SER
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SN54HC165, SN74HC165 8 BIT PARALLEL LOAD SHIFT REGISTERS
SCLS116E - DECEMBER 1982 - REVISED SEPTEMBER 2003
description/ordering information (continued)
Clocking is accomplished by a low-to-high transition of the clock (CLK) input while SH/LD is held high and CLK INH is held low. The functions of CLK and CLK INH are interchangeable. Since a low CLK and a low-to-high transition of CLK INH also accomplish clocking, CLK INH should be changed to the high level only while CLK is high. Parallel loading is inhibited when SH/LD is held high. While SH/LD is low, the parallel inputs to the register are enabled independently of the levels of the CLK, CLK INH, or serial (SER) inputs.
FUNCTION TABLE INPUTS SH/LD L H H H H FUNCTION CLK X H X L CLK INH X X H Parallel load No change No change Shift
L Shift Shift = content of each internal register shifts toward serial output QH. Data at SER is shifted into the first register.
logic diagram (positive logic)
A SH/LD CLK INH CLK SER 1 15 2 10
S C1 1D R S C1 1D R S C1 1D R S C1 1D R S C1 1D R S C1 1D R S C1 1D R S C1 1D R
B 11 12
C 13
D 14
E 3
F 4
G 5
H 6
9
QH
7
QH
Pin numbers shown are for the D, DB, J, N, NS, PW, and W packages.
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SN54HC165, SN74HC165 8 BIT PARALLEL LOAD SHIFT REGISTERS
SCLS116E - DECEMBER 1982 - REVISED SEPTEMBER 2003
typical shift, load, and inhibit sequence
CLK
CLK INH SER L
SH/LD A H L H L H
B C Data Inputs
D E
F G H QH QH
L H H H L Inhibit Load H L L H H L L H H L L H H L
Serial Shift
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SN54HC165, SN74HC165 8 BIT PARALLEL LOAD SHIFT REGISTERS
SCLS116E - DECEMBER 1982 - REVISED SEPTEMBER 2003
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Package thermal impedance, JA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
SN54HC165 MIN VCC VIH Supply voltage VCC = 2 V VCC = 4.5 V VCC = 6 V VCC = 2 V VIL VI VO t/v Low-level input voltage Input voltage Output voltage VCC = 2 V VCC = 4.5 V VCC = 6 V VCC = 4.5 V VCC = 6 V 0 0 2 1.5 3.15 4.2 0.5 1.35 1.8 VCC VCC 1000 500 400 0 0 NOM 5 MAX 6 SN74HC165 MIN 2 1.5 3.15 4.2 0.5 1.35 1.8 VCC VCC 1000 500 400 ns V V V V NOM 5 MAX 6 UNIT V
High-level input voltage
Input transition rise/fall time
TA Operating free-air temperature -55 125 -40 85 C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. If this device is used in the threshold region (from VILmax = 0.5 V to VIHmin = 1.5 V), there is a potential to go into the wrong state from induced grounding, causing double clocking. Operating with the inputs at tt = 1000 ns and VCC = 2 V does not damage the device; however, functionally, the CLK inputs are not ensured while in the shift, count, or toggle operating modes.
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SN54HC165, SN74HC165 8 BIT PARALLEL LOAD SHIFT REGISTERS
SCLS116E - DECEMBER 1982 - REVISED SEPTEMBER 2003
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC 2V IOH = -20 A VOH VI = VIH or VIL IOH = -4 mA IOH = -5.2 mA IOL = 20 A VOL VI = VIH or VIL IOL = 4 mA IOL = 5.2 mA II ICC Ci VI = VCC or 0 VI = VCC or 0, IO = 0 4.5 V 6V 4.5 V 6V 2V 4.5 V 6V 4.5 V 6V 6V 6V 2 V to 6 V 3 MIN 1.9 4.4 5.9 3.98 5.48 TA = 25C TYP MAX 1.998 4.499 5.999 4.3 5.8 0.002 0.001 0.001 0.17 0.15 0.1 0.1 0.1 0.1 0.26 0.26 100 8 10 SN54HC165 MIN 1.9 4.4 5.9 3.7 5.2 0.1 0.1 0.1 0.4 0.4 1000 160 10 MAX SN74HC165 MIN 1.9 4.4 5.9 3.84 5.34 0.1 0.1 0.1 0.33 0.33 1000 80 10 nA A pF V V MAX UNIT
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SN54HC165, SN74HC165 8 BIT PARALLEL LOAD SHIFT REGISTERS
SCLS116E - DECEMBER 1982 - REVISED SEPTEMBER 2003
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
VCC 2V fclock Clock frequency 4.5 V 6V 2V SH/LD low tw Pulse duration CLK high or low 4.5 V 6V 2V 4.5 V 6V 2V SH/LD high before CLK 4.5 V 6V 2V SER before CLK 4.5 V 6V 2V tsu Setup time CLK INH low before CLK 4.5 V 6V 2V CLK INH high before CLK 4.5 V 6V 2V Data before SH/LD 4.5 V 6V 2V SER data after CLK th Hold time PAR data after SH/LD 4.5 V 6V 2V 4.5 V 6V 80 16 14 80 16 14 80 16 14 40 8 7 100 20 17 40 8 7 100 20 17 5 5 5 5 5 5 TA = 25C MIN MAX 6 31 36 120 24 20 120 24 20 120 24 20 60 12 10 150 30 25 60 12 10 150 30 26 5 5 5 5 5 5 SN54HC165 MIN MAX 4.2 21 25 100 20 17 100 20 17 100 20 17 50 10 9 125 25 21 50 10 9 125 25 21 5 5 5 5 5 5 ns ns ns SN74HC165 MIN MAX 5 25 29 MHz UNIT
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SN54HC165, SN74HC165 8 BIT PARALLEL LOAD SHIFT REGISTERS
SCLS116E - DECEMBER 1982 - REVISED SEPTEMBER 2003
switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER FROM (INPUT) TO (OUTPUT) VCC 2V fmax 4.5 V 6V 2V SH/LD QH or QH 4.5 V 6V 2V tpd CLK QH or QH 4.5 V 6V 2V H QH or QH 4.5 V 6V 2V tt Any 4.5 V 6V MIN 6 31 36 TA = 25C TYP MAX 13 50 62 80 20 16 75 15 13 75 15 13 38 8 6 150 30 26 150 30 26 150 30 26 75 15 13 SN54HC165 MIN 4.2 21 25 225 45 38 225 45 38 225 45 38 110 22 19 MAX SN74HC165 MIN 5 25 29 190 38 32 190 38 32 190 38 32 95 19 16 ns ns MHz MAX UNIT
operating characteristics, TA = 25C
PARAMETER Cpd Power dissipation capacitance TEST CONDITIONS No load TYP 75 UNIT pF
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SN54HC165, SN74HC165 8 BIT PARALLEL LOAD SHIFT REGISTERS
SCLS116E - DECEMBER 1982 - REVISED SEPTEMBER 2003
PARAMETER MEASUREMENT INFORMATION
High-Level Pulse VCC 50% tw Low-Level Pulse VCC 50% 50% 0V LOAD CIRCUIT VOLTAGE WAVEFORMS PULSE DURATIONS VCC 50% tPLH Reference Input tsu Data Input 50% 10% 90% 50% th 90% VCC 50% 10% 0 V tf Out-of-Phase Output VCC 0V In-Phase Output 50% 10% tPHL 90% 50% 10% tf 90% tr tPLH 50% 10% 90% tr 50% 0V tPHL 90% VOH 50% 10% VOL tf VOH VOL 50% 0V
From Output Under Test
Test Point CL = 50 pF (see Note A)
Input
tr
VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
NOTES: A. CL includes probe and test-fixture capacitance. B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr = 6 ns, tf = 6 ns. C. For clock inputs, fmax is measured when the input duty cycle is 50%. D. The outputs are measured one at a time with one input transition per measurement. E. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
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MECHANICAL DATA
MCFP004A- JANUARY 1995 - REVISED FEBRUARY 2002
W (R-GDFP-F16)
CERAMIC DUAL FLATPACK
Base and Seating Plane
0.045 (1,14) 0.026 (0,66)
0.285 (7,24) 0.245 (6,22)
0.006 (0,15) 0.080 (2,03) 0.055 (1,40) 0.305 (7,75) MAX 1 16 0.019 (0,48) 0.015 (0,38) 0.004 (0,10)
0.050 (1,27)
0.430 (10,92) 0.370 (9,40)
0.005 (0,13) MIN 4 Places
8 0.360 (9,14) 0.250 (6,35)
9 0.360 (9,14) 0.250 (6,35) 4040180-3 / C 02/02
NOTES: A. B. C. D. E.
All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. Index point is provided on cap for terminal identification only. Falls within MIL STD 1835 GDFP-1F16 and JEDEC MO-092AC
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1
MECHANICAL DATA
MLCC006B - OCTOBER 1996
FK (S-CQCC-N**)
28 TERMINAL SHOWN
LEADLESS CERAMIC CHIP CARRIER
18
17
16
15
14
13
12
NO. OF TERMINALS ** 11 10 28 9 8 7 6 68 5 84 44 52 20
A MIN 0.342 (8,69) 0.442 (11,23) 0.640 (16,26) 0.739 (18,78) 0.938 (23,83) 1.141 (28,99) MAX 0.358 (9,09) 0.458 (11,63) 0.660 (16,76) 0.761 (19,32) 0.962 (24,43) 1.165 (29,59) MIN 0.307 (7,80) 0.406 (10,31) 0.495 (12,58) 0.495 (12,58) 0.850 (21,6) 1.047 (26,6)
B MAX 0.358 (9,09) 0.458 (11,63) 0.560 (14,22) 0.560 (14,22) 0.858 (21,8) 1.063 (27,0)
19 20 21 B SQ 22 A SQ 23 24 25
26
27
28
1
2
3
4 0.080 (2,03) 0.064 (1,63) 0.020 (0,51) 0.010 (0,25)
0.020 (0,51) 0.010 (0,25)
0.055 (1,40) 0.045 (1,14)
0.045 (1,14) 0.035 (0,89)
0.028 (0,71) 0.022 (0,54) 0.050 (1,27)
0.045 (1,14) 0.035 (0,89)
4040140 / D 10/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a metal lid. The terminals are gold plated. Falls within JEDEC MS-004
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1
MECHANICAL
MPDI002C - JANUARY 1995 - REVISED DECEMBER 20002
N (R-PDIP-T**)
16 PINS SHOWN
PLASTIC DUAL-IN-LINE PACKAGE
PINS ** DIM A 16 9 A MAX
14 0.775 (19,69) 0.745 (18,92)
16 0.775 (19,69) 0.745 (18,92)
18 0.920 (23,37) 0.850 (21,59)
20 1.060 (26,92) 0.940 (23,88)
A MIN
0.260 (6,60) 0.240 (6,10)
C
MS-100 VARIATION
AA
BB
AC
AD
1 0.070 (1,78) 0.045 (1,14) D
8
0.045 (1,14) 0.030 (0,76) D
0.020 (0,51) MIN
0.325 (8,26) 0.300 (7,62) 0.015 (0,38) 0.200 (5,08) MAX Seating Plane 0.125 (3,18) MIN 0.010 (0,25) NOM Gauge Plane
0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0.010 (0,25) M
0.430 (10,92) MAX
14/18 PIN ONLY 20 pin vendor option
D 4040049/E 12/2002
NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001, except 18 and 20 pin minimum body lrngth (Dim A). D. The 20 pin end lead shoulder width is a vendor option, either half or full width.
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1
MECHANICAL DATA
MSOI002B - JANUARY 1995 - REVISED SEPTEMBER 2001
D (R-PDSO-G**)
8 PINS SHOWN 0.050 (1,27) 8 5 0.020 (0,51) 0.014 (0,35) 0.010 (0,25)
PLASTIC SMALL-OUTLINE PACKAGE
0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81)
0.008 (0,20) NOM
Gage Plane 1 A 4 0- 8 0.044 (1,12) 0.016 (0,40)
0.010 (0,25)
Seating Plane 0.069 (1,75) MAX 0.010 (0,25) 0.004 (0,10) 0.004 (0,10)
PINS ** DIM A MAX A MIN
8 0.197 (5,00) 0.189 (4,80)
14 0.344 (8,75) 0.337 (8,55)
16 0.394 (10,00) 0.386 (9,80)
4040047/E 09/01 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). Falls within JEDEC MS-012
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1
MECHANICAL DATA
MSSO002E - JANUARY 1995 - REVISED DECEMBER 2001
DB (R-PDSO-G**)
28 PINS SHOWN 0,65 28 0,38 0,22 15 0,15 M
PLASTIC SMALL-OUTLINE
0,25 0,09 5,60 5,00 8,20 7,40
Gage Plane 1 A 14 0- 8 0,25 0,95 0,55
Seating Plane 2,00 MAX 0,05 MIN 0,10
PINS ** DIM A MAX
14
16
20
24
28
30
38
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30 4040065 /E 12/01
NOTES: A. B. C. D.
All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150
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1
MECHANICAL DATA
MTSS001C - JANUARY 1995 - REVISED FEBRUARY 1999
PW (R-PDSO-G**)
14 PINS SHOWN
PLASTIC SMALL-OUTLINE PACKAGE
0,65 14 8
0,30 0,19
0,10 M
0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 A 7 0- 8 0,75 0,50
Seating Plane 1,20 MAX 0,15 0,05 0,10
PINS ** DIM A MAX
8
14
16
20
24
28
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153
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1
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